The invention relates to a power module.
Power electronic components such as switchable semiconductors and diodes are often combined in power modules in order to implement certain topologies such as pulse converters and/or power rectifiers in one module. The individual components in such a module are connected by bonding wires that lead from one power component, for example a switchable semiconductor chip, in particular an Insulated Gate Bipolar Transistor chip (IGBT), to another power component, for example a diode chip, or to a printed conductor on a substrate of this power module.
These bonding wires have the following disadvantages however:                The inductance introduced into the module by each bond connection is relatively high, whereby the individual semiconductor chips are subject to a higher voltage load during a switching action. It is not possible to reduce significantly this parasitic inductance for geometric and fabrication reasons.        The current density at the bonding point itself is relatively high, reducing the reliability of the connection.        It is almost impossible to implement more complex topologies by this fabrication technique because of the crossover of bond connections.        
U.S. Pat. No. 5,532,512 discloses a power semiconductor device, which comprises a plurality of semiconductor devices that are stacked one above the other on a substrate. Each semiconductor device comprises just one semiconductor chip that is provided with contact pads. These contact pads are soldered to metallizations on the semiconductor chip. In order to produce a half-bridge topology, two such semiconductor chips are required. These two semiconductor chips are stacked on top of each other and soldered together. This stack of semiconductor chips is electrically connected to an electrically conducting layer of a substrate. Other topologies (parallel connection of a plurality of semiconductor chips) can be achieved by such a fabricated semiconductor chip.
WO 03/030247 A2 discloses a power module in which at least one semiconductor chip is bonded to an electrically conducting layer of a substrate. A film made of electrically insulating material lies in close contact with the surfaces of the semiconductor chip, the electrically conducting layer and the substrate. To enable contact to be made with the two contacts of the semiconductor chip, this film has at least one window, which exposes the contact surface of a contact of the semiconductor chip. A layer made of electrically conducting material is applied over the whole surface of this film including its windows. Planar interconnects are made from this electrically conducting layer by a photolithographic process. In this embodiment, the film is laminated on.
In this power module, all active and passive semiconductor chips are arranged side by side on a substrate and connected together electrically by means of planar interconnects. To implement certain topologies such,as pulse converters and/or power rectifiers in one module, such a module will have a very large surface area.
The object of the invention is to develop a power module of the type cited in the introduction in such a way that it is compact.